GB1360470A – Computer input-output chaining system
– Google Patents
GB1360470A – Computer input-output chaining system
– Google Patents
Computer input-output chaining system
Info
Publication number
GB1360470A
GB1360470A
GB5620171A
GB5620171A
GB1360470A
GB 1360470 A
GB1360470 A
GB 1360470A
GB 5620171 A
GB5620171 A
GB 5620171A
GB 5620171 A
GB5620171 A
GB 5620171A
GB 1360470 A
GB1360470 A
GB 1360470A
Authority
GB
United Kingdom
Prior art keywords
address
block
data
transfer
controller
Prior art date
1971-03-11
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5620171A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-03-11
Filing date
1971-12-03
Publication date
1974-07-17
1971-12-03
Application filed by RCA Corp
filed
Critical
RCA Corp
1974-07-17
Publication of GB1360470A
publication
Critical
patent/GB1360470A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/14—Handling requests for interconnection or transfer
G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F13/10—Program control for peripheral devices
G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Abstract
1360470 Data transfer systems RCA CORPORATION 3 Dec 1971 [11 March 1971] 56201/71 Heading G4A Blocks of data words are stored in corresponding blocks of memory locations, which blocks of locations may be located anywhere within the memory, a dedicated counter initially stores the address of a first location in a list of addresses which is used to sequentially address a plurality of data address counters each of which initially stores the memory location address of the first data word of a corresponding block and is used to sequentially address the words of that block. After a data channel between the memory and an I/O device via an I/O controller has been established by a processor, transfer of a plurality of blocks of data words can thus take place in a predetermined order without further recourse to the processor (called chaining). Output transfer (1).-A chaining output command from the processor over bus 5 to CU in the I/O controller causes FF-I to be set and FF-V to be reset. (2) CU sends a data channel request to the processor which grants the request to establish the channel. (3) A wired-in address WA is sent over address bus AB to the processor to address the dedicated counter DC, Fig. 1b, corresponding to the I/O controller. All counters shown are in fact memory word locations. Counter DC comprises a pair of counters LAC, BC which are addressed sequentially. The addressed counter LAC contains the address of the first word in a list LA and this word which represents the address of a pair of counters PC for block A, is transferred over data bus DB to an address register AR in the I/O controller. LAC is then incremented and BC decremented from their initial values determined by the program. FF-II is then set and FF-III reset. (4) Steps (2), (3) are repeated, but now, since FF-II is set, the address in AR is used to address the counter PC for block A, this counter comprising the sequentially addressed counters DAC, WC. Counter DAC contains the address of the first data word in block A and this word is addressed and transferred over DB, through gate K to the I/O device which returns a data accepted signal. DAC is incremented and WC decremented for each word transferred until WC reaches zero and produces an overflow signal to set FF-III followed by reset of FF-II in the I/O controller. (5) Steps (2) and (3) are repeated to again transfer the wired-in address WA to address LAC which this time addresses the second word in list LA to obtain the address of counter PC for block B and transfer it to address register AR. (6) Step (4) is repeated to transfer block B to the I/O device. A further repetition of steps (2)-(4) causes transfer of block C, but during this operation BC overflows to set FF-IV to terminate the operation when the last data word of block C has been accepted by the I/O device. An earlier termination may be caused if any data word in blocks A-C contains an end of text control character EXT. In addition, less than a complete block may be accessed by including a U.S. control character in the last data word to be transferred from that block, monitor M responding to this character to initiate addressing of the next block or termination of the operation. Operation with more than one I/O controller.- A separate counter DC, PC and list LA is dedicated to each controller, this enabling all controllers to share common data block locations in memory, e.g. one controller may receive blocks A, B and D while another receives blocks A, D and C in that order. Input transfer.-A data channel request is sent to the processor from the I/O controller in response to a data ready signal from the I/O device. FF-V is set to close output gate K and enable input gate Y. Transfer proceeds in a similar manner to the output operation (in the reverse direction), but provision is made to interrupt the processor if the available space in memory is exhausted whereby the processor can allocate more space before the transfer is continued. Normal transfer without chaining.-In this mode the I/O controller is only able to sequentially address the locations of one data block, each new block requiring a fresh initialization procedure to be performed.
GB5620171A
1971-03-11
1971-12-03
Computer input-output chaining system
Expired
GB1360470A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US12328171A
1971-03-11
1971-03-11
Publications (1)
Publication Number
Publication Date
GB1360470A
true
GB1360470A
(en)
1974-07-17
Family
ID=22407749
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB5620171A
Expired
GB1360470A
(en)
1971-03-11
1971-12-03
Computer input-output chaining system
Country Status (10)
Country
Link
US
(1)
US3728682A
(en)
JP
(1)
JPS521830B1
(en)
AU
(1)
AU464225B2
(en)
CA
(1)
CA951831A
(en)
DE
(1)
DE2161213B2
(en)
ES
(1)
ES397793A1
(en)
FR
(1)
FR2129340A5
(en)
GB
(1)
GB1360470A
(en)
IT
(1)
IT955076B
(en)
NL
(1)
NL7116987A
(en)
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4459655A
(en)
*
1980-03-27
1984-07-10
Willemin Machines S.A.
Control system for a machine or for an installation
Families Citing this family (7)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3829837A
(en)
*
1971-06-24
1974-08-13
Honeywell Inf Systems
Controller for rotational storage device having linked information organization
US4369494A
(en)
*
1974-12-09
1983-01-18
Compagnie Honeywell Bull
Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system
US4177512A
(en)
*
1976-03-12
1979-12-04
Burroughs Corporation
Soft input/output auto poll system
US4065810A
(en)
*
1977-01-26
1977-12-27
International Business Machines Corporation
Data transfer system
US4296466A
(en)
*
1978-01-23
1981-10-20
Data General Corporation
Data processing system including a separate input/output processor with micro-interrupt request apparatus
EP0199053B1
(en)
*
1985-03-20
1993-07-28
Hitachi, Ltd.
Input/output control system
JP3549003B2
(en)
*
1993-08-31
2004-08-04
株式会社日立製作所
Information sending device and information sending / receiving system
Family Cites Families (8)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3488633A
(en)
*
1964-04-06
1970-01-06
Ibm
Automatic channel apparatus
US3406380A
(en)
*
1965-11-26
1968-10-15
Burroughs Corp
Input-output data service computer
US3411143A
(en)
*
1966-01-13
1968-11-12
Ibm
Instruction address control by peripheral devices
US3409880A
(en)
*
1966-05-26
1968-11-05
Gen Electric
Apparatus for processing data records in a computer system
US3475729A
(en)
*
1966-05-27
1969-10-28
Gen Electric
Input/output control apparatus in a computer system
US3546677A
(en)
*
1967-10-02
1970-12-08
Burroughs Corp
Data processing system having tree structured stack implementation
US3559187A
(en)
*
1968-11-13
1971-01-26
Gen Electric
Input/output controller with linked data control words
US3588831A
(en)
*
1968-11-13
1971-06-28
Honeywell Inf Systems
Input/output controller for independently supervising a plurality of operations in response to a single command
1971
1971-03-11
US
US00123281A
patent/US3728682A/en
not_active
Expired – Lifetime
1971-11-29
CA
CA128,883,A
patent/CA951831A/en
not_active
Expired
1971-12-03
GB
GB5620171A
patent/GB1360470A/en
not_active
Expired
1971-12-09
DE
DE2161213A
patent/DE2161213B2/en
not_active
Withdrawn
1971-12-09
ES
ES397793A
patent/ES397793A1/en
not_active
Expired
1971-12-10
FR
FR7144514A
patent/FR2129340A5/fr
not_active
Expired
1971-12-10
NL
NL7116987A
patent/NL7116987A/xx
unknown
1971-12-10
JP
JP46100613A
patent/JPS521830B1/ja
active
Pending
1971-12-10
AU
AU36735/71A
patent/AU464225B2/en
not_active
Expired
1971-12-10
IT
IT32247/71A
patent/IT955076B/en
active
Cited By (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4459655A
(en)
*
1980-03-27
1984-07-10
Willemin Machines S.A.
Control system for a machine or for an installation
Also Published As
Publication number
Publication date
AU464225B2
(en)
1975-08-21
ES397793A1
(en)
1974-05-16
JPS521830B1
(en)
1977-01-18
FR2129340A5
(en)
1972-10-27
NL7116987A
(en)
1972-09-13
US3728682A
(en)
1973-04-17
IT955076B
(en)
1973-09-29
DE2161213B2
(en)
1974-02-28
DE2161213A1
(en)
1972-11-23
CA951831A
(en)
1974-07-23
AU3673571A
(en)
1973-06-14
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Legal Events
Date
Code
Title
Description
1974-11-27
PS
Patent sealed [section 19, patents act 1949]
1978-07-12
PCNP
Patent ceased through non-payment of renewal fee
