GB1363154A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1363154A – Data converter for a computer systems
– Google Patents

GB1363154A – Data converter for a computer systems
– Google Patents
Data converter for a computer systems

Info

Publication number
GB1363154A

GB1363154A
GB4038871A
GB4038871A
GB1363154A
GB 1363154 A
GB1363154 A
GB 1363154A
GB 4038871 A
GB4038871 A
GB 4038871A
GB 4038871 A
GB4038871 A
GB 4038871A
GB 1363154 A
GB1363154 A
GB 1363154A
Authority
GB
United Kingdom
Prior art keywords
bits
numeric
output
byte
flip
Prior art date
1970-08-28
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB4038871A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1970-08-28
Filing date
1971-08-27
Publication date
1974-08-14

1970-08-28
Priority claimed from JP7540670A
external-priority
patent/JPS4947969B1/ja

1971-08-27
Application filed by Nippon Electric Co Ltd
filed
Critical
Nippon Electric Co Ltd

1974-08-14
Publication of GB1363154A
publication
Critical
patent/GB1363154A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

1363154 Data packing NIPPON ELECTRIC CO Ltd 27 Aug 1971 [28 Aug 1970] 40388/71 Heading G4A [Also in Division H4] A hardware data conversion apparatus is arranged to pack numeric and alpha-numeric n bit characters into m bit bytes and to unpack m bit bytes into n bit numeric and alpha-numeric characters. In an embodiment the numeric characters consist of four significant (BCD) bits and two non-significant bits which identify the character as being numeric and the alpha-numeric characters consist of six significant bits. Successive characters are packed into eight bit bytes such that a byte in which the last four bits are all «1» is a single numeric character given by bits 1-4, a byte in which bits 3 and 4 are both «1» is a single alpha-numeric character given by bits 1, 2 and 5-8, and any other byte is two numeric characters given by bits 1-4 and 5-8 respectively. Data, e.g. from a computer, is fed into a six bit register, the last two bits being zero for a numeric character. A gate circuit generates an output on line 63 in response to those last two bits to set and reset flip-flop 34, Fig. 6A, according to whether the data represents a numeric or alpha-numeric character respectively. The flipflop is actually set or reset on the occurrence of an output on line 101 from multivibrator (MV) T1 which is energized by a «start conversion» signal on line 64. The output of T1 triggers T2 whose output is fed to the AND gates 124-128 and to gate 107. Assuming that the data is a numeric character, flip-flop 34 will be set and its output is passed to gates 124 and 125 and, via OR gate 123, to AND gate 107, which, via OR gate 109 triggers T3. Meanwhile, AND gate 124 will conduct (all its inputs, i.e. the outputs of T2, set output of 34, and reset output of 35, being 1) and generate a signal M1 which is passed to a gating system, Fig. 9. It will be apparent from Fig. 9 that the signal M1 causes the first four bits of the six bits being converted to be loaded into the first four bit positions 1, 2, 4, 8 of a byte register (not shown). When T3 triggers its output enables gates 117 and 118, causing flip-flop 35 to assume the state of flipflop 34, i.e. set, and the six bit register to be loaded with the next character by means of a signal in one of the group of lines 66. T3 triggers T4, whose output resets flip-flop 34, but is blocked at AND gate 138 due to the state of flip-flop 35. The process then repeats. However, if the new character is alpha numeric (i.e. six bits) it will not fit into the remaining byte positions and the system operates (by having flip-flop 34 reset) to generate by means of gate 127 a signal M4 which loads four 1’s into the remaining byte positions, see Fig. 9. If the next character is numeric a signal M2 is produced by gate 125 and the relevant four bits are loaded into the remaining byte positions. Following the filling of the remaining bit position of the byte a signal 75 is generated either in response to the output of T4 together with a reset output from flip-flop 35 or to the output of T2 together with a set output from flip-flop 34 and a set output of flip-flop 35. The signal 75 causes the assembled byte to be loaded into an output register, the byte register being cleared. The operation is analogous for an alpha-numeric character, flipflop 34 remaining reset due to the presence of a 1 bit in one of the last two positions of the six bit register. The reverse conversion is performed by the device shown in Fig. 6B. In response to a start signal multivibrator S1 is triggered. The output of S1 by means of a gating circuit sets flipflop 37 if the last four bits of the byte being converted are 1’s, sets flip-flop 38 if bits 3 and 4 of the byte are 1’s, and sets neither flip-flop otherwise. In a manner analogous to that of Fig. 6A, signals N1, N2 and N3 are generated, in response to the triggering of the multivibrators S1-S6 and the states of flip-flops 37 and 38, to load various bits from the byte register into a six bit register, see Fig. 10. The six bit register contents are transmitted and the register cleared in response to signals on line 65. The possibilities of using characters represented by different numbers of bits and the inclusion of parity bits are mentioned.

GB4038871A
1970-08-28
1971-08-27
Data converter for a computer systems

Expired

GB1363154A
(en)

Applications Claiming Priority (2)

Application Number
Priority Date
Filing Date
Title

JP7540670A

JPS4947969B1
(en)

1970-08-28
1970-08-28

US17384971A

1971-08-23
1971-08-23

Publications (1)

Publication Number
Publication Date

GB1363154A
true

GB1363154A
(en)

1974-08-14

Family
ID=26416543
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB4038871A
Expired

GB1363154A
(en)

1970-08-28
1971-08-27
Data converter for a computer systems

Country Status (3)

Country
Link

US
(1)

US3701893A
(en)

DE
(1)

DE2142948C3
(en)

GB
(1)

GB1363154A
(en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3872442A
(en)

1972-12-14
1975-03-18
Sperry Rand Corp
System for conversion between coded byte and floating point format

US3914586A
(en)

1973-10-25
1975-10-21
Gen Motors Corp
Data compression method and apparatus

US3930232A
(en)

1973-11-23
1975-12-30
Raytheon Co
Format insensitive digital computer

US4574362A
(en)

1982-04-12
1986-03-04
Tektronix, Inc.
Block mode digital signal conditioning method and apparatus

US5237701A
(en)

1989-03-31
1993-08-17
Ampex Systems Corporation
Data unpacker using a pack ratio control signal for unpacked parallel fixed m-bit width into parallel variable n-bit width word

FR2709892B1
(en)

1993-09-09
1995-10-13
Alcatel Radiotelephone

Method for compressing and decompressing a stream of hexadecimal numeric values coded in ASCII.

JP2002366426A
(en)

2001-06-11
2002-12-20
Mitsumi Electric Co Ltd
Program executing device and program executing method

Family Cites Families (2)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US3560639A
(en)

1966-10-03
1971-02-02
Xerox Corp
Cascade run length encoding technique

GB1250908A
(en)

1968-12-13
1971-10-27

1971

1971-08-23
US
US173849A
patent/US3701893A/en
not_active
Expired – Lifetime

1971-08-27
GB
GB4038871A
patent/GB1363154A/en
not_active
Expired

1971-08-27
DE
DE2142948A
patent/DE2142948C3/en
not_active
Expired

Also Published As

Publication number
Publication date

DE2142948C3
(en)

1974-04-11

US3701893A
(en)

1972-10-31

DE2142948B2
(en)

1973-09-20

DE2142948A1
(en)

1972-03-23

Información de contacto