GB1374357A – Data transmission systems
– Google Patents
GB1374357A – Data transmission systems
– Google Patents
Data transmission systems
Info
Publication number
GB1374357A
GB1374357A
GB887072A
GB887072A
GB1374357A
GB 1374357 A
GB1374357 A
GB 1374357A
GB 887072 A
GB887072 A
GB 887072A
GB 887072 A
GB887072 A
GB 887072A
GB 1374357 A
GB1374357 A
GB 1374357A
Authority
GB
United Kingdom
Prior art keywords
bits
block
signals
synchronization
correct
Prior art date
1971-03-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB887072A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-03-18
Filing date
1972-02-25
Publication date
1974-11-20
1971-03-18
Priority claimed from DE19712113018
external-priority
patent/DE2113018C/en
1972-02-25
Application filed by Siemens AG
filed
Critical
Siemens AG
1974-11-20
Publication of GB1374357A
publication
Critical
patent/GB1374357A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
H—ELECTRICITY
H04—ELECTRIC COMMUNICATION TECHNIQUE
H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L7/00—Arrangements for synchronising receiver with transmitter
H04L7/04—Speed or phase control by synchronisation signals
H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Abstract
1374357 Digital transmission; synchronization SIEMENS AG 25 Feb 1972 [18 March 1971 25 Jan 1972] 8870/72 Heading H4P In a synchronizing arrangement in which redundant bits are utilized, the redundant bits may also be used for synchronization of bit fault recognition. The blocks are received into a shift register having test circuits connected to individual cells which emit test signals on application of a series of timing signals if the bits in the shift register belong to the same block, there being as many trains of timing signals as possible data blocks. The outputs of the test circuits are passed to counters connected to a logic arrangement which determines which one of the timing trains are relative to the correct block. Preferably as many test circuits are provided as possible block arrangements. In a simple case each block B = 4 bits, the first and fourth being redundant bits which serve for synchronization. Trigger stages K1-K4 form a shift register having a test circuit P1-P4 connected thereto and a correct block arrangement exists when bit A1 = 0 and A4 = 1; the test circuits check bits in stages K1-K4 at different times. When correct lines h1-h4 emit Is or when incorrect this is signalled on lines g1-g4. Timing signals TB1-TB4 from LOG are supplied to terminals c of P1-P4. When inputs to half adder F are equal a O is emitted to AND gate U1 resetting counter AZ, also through inverter N1 to AND gate U2 which steps AZ forward; at max. count nAZ-# 1. Counters Z1-Z4 are stepped by signals a and reset by b ; at maximum count k a 1 is issued to LOG from which signals TA, TS, TB1-TB4 are derived. If the data bits A2, A3 have the values 0, 1, at time t3 a 1 is emitted from P3 through line h3 to Z3 thus a correct block arrangement is signalled. On the other hand incorrect blocks have no effect because counters are reset before arrival of the k counting pulse. Preferably A1, A4 are parity bits calculated from bits A2, A3 hence may be used for error correction in addition to block synchronization.
GB887072A
1971-03-18
1972-02-25
Data transmission systems
Expired
GB1374357A
(en)
Applications Claiming Priority (2)
Application Number
Priority Date
Filing Date
Title
DE19712113018
DE2113018C
(en)
1971-03-18
Circuit arrangement for establishing the synchronization of transmitting and receiving devices when transmitting binary data blocks
DE19722203414
DE2203414C3
(en)
1971-03-18
1972-01-25
Method and circuit arrangement for establishing synchronization of transmitting and receiving devices during the transmission of data blocks
Publications (1)
Publication Number
Publication Date
GB1374357A
true
GB1374357A
(en)
1974-11-20
Family
ID=25760817
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB887072A
Expired
GB1374357A
(en)
1971-03-18
1972-02-25
Data transmission systems
Country Status (10)
Country
Link
JP
(1)
JPS5250482B1
(en)
BE
(1)
BE780886A
(en)
CH
(1)
CH539988A
(en)
DE
(1)
DE2203414C3
(en)
FR
(1)
FR2130479B1
(en)
GB
(1)
GB1374357A
(en)
IT
(1)
IT950193B
(en)
LU
(1)
LU64976A1
(en)
NL
(1)
NL170794C
(en)
SE
(1)
SE362719B
(en)
Cited By (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE3238157A1
(en)
*
1981-10-15
1983-05-05
Victor Company Of Japan, Ltd., Yokohama, Kanagawa
METHOD AND CIRCUIT FOR DETERMINING SYNCHRONIZATION
US4425645A
(en)
1981-10-15
1984-01-10
Sri International
Digital data transmission with parity bit word lock-on
Families Citing this family (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3950616A
(en)
*
1975-04-08
1976-04-13
Bell Telephone Laboratories, Incorporated
Alignment of bytes in a digital data bit stream
1972
1972-01-25
DE
DE19722203414
patent/DE2203414C3/en
not_active
Expired
1972-02-25
GB
GB887072A
patent/GB1374357A/en
not_active
Expired
1972-02-29
CH
CH282872A
patent/CH539988A/en
not_active
IP Right Cessation
1972-03-15
IT
IT2184872A
patent/IT950193B/en
active
1972-03-16
LU
LU64976D
patent/LU64976A1/xx
unknown
1972-03-16
NL
NL7203515A
patent/NL170794C/en
not_active
IP Right Cessation
1972-03-17
BE
BE780886A
patent/BE780886A/en
not_active
IP Right Cessation
1972-03-17
SE
SE346372A
patent/SE362719B/xx
unknown
1972-03-18
JP
JP2801272A
patent/JPS5250482B1/ja
active
Pending
1972-03-20
FR
FR7209719A
patent/FR2130479B1/fr
not_active
Expired
Cited By (3)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
DE3238157A1
(en)
*
1981-10-15
1983-05-05
Victor Company Of Japan, Ltd., Yokohama, Kanagawa
METHOD AND CIRCUIT FOR DETERMINING SYNCHRONIZATION
US4425645A
(en)
1981-10-15
1984-01-10
Sri International
Digital data transmission with parity bit word lock-on
US4524445A
(en)
*
1981-10-15
1985-06-18
Victor Company Of Japan, Limited
Method and circuit arrangement for synchronous detection
Also Published As
Publication number
Publication date
LU64976A1
(en)
1972-12-07
DE2203414A1
(en)
1973-08-02
DE2203414C3
(en)
1979-06-07
DE2203414B2
(en)
1978-10-12
FR2130479A1
(en)
1972-11-03
CH539988A
(en)
1973-07-31
JPS5250482B1
(en)
1977-12-24
NL170794B
(en)
1982-07-16
NL170794C
(en)
1982-12-16
IT950193B
(en)
1973-06-20
SE362719B
(en)
1973-12-17
FR2130479B1
(en)
1977-09-02
BE780886A
(en)
1972-09-18
NL7203515A
(en)
1972-09-20
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Legal Events
Date
Code
Title
Description
1975-04-03
PS
Patent sealed
1984-10-31
PCNP
Patent ceased through non-payment of renewal fee
