GB1414958A – Binary arithmetic units
– Google Patents
GB1414958A – Binary arithmetic units
– Google Patents
Binary arithmetic units
Info
Publication number
GB1414958A
GB1414958A
GB5112271A
GB5112271A
GB1414958A
GB 1414958 A
GB1414958 A
GB 1414958A
GB 5112271 A
GB5112271 A
GB 5112271A
GB 5112271 A
GB5112271 A
GB 5112271A
GB 1414958 A
GB1414958 A
GB 1414958A
Authority
GB
United Kingdom
Prior art keywords
bit
row
cells
mantissa
exponent
Prior art date
1971-11-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5112271A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Research Development Corp UK
Original Assignee
National Research Development Corp UK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1971-11-03
Filing date
1971-11-03
Publication date
1975-11-19
1971-11-03
Application filed by National Research Development Corp UK
filed
Critical
National Research Development Corp UK
1971-11-03
Priority to GB5112271A
priority
Critical
patent/GB1414958A/en
1975-11-19
Publication of GB1414958A
publication
Critical
patent/GB1414958A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F7/487—Multiplying; Dividing
G06F7/4876—Multiplying
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
G06F7/499—Denomination or exception handling, e.g. rounding or overflow
G06F7/49905—Exception handling
G06F7/4991—Overflow or underflow
Abstract
1414958 Digital arithmetic units NATIONAL RESEARCH DEVELOPMENT CORP 30 Jan 1973 [3 Nov 1971] 51122/71 Heading G4A A binary arithmetic unit comprises a rectangular array of cells, each as in Fig. 4, for performing multiplication or addition. The numbers are each in the form of a mantissa and exponent. Multiplication takes place by repeated addition and shift. If the numbers are such that overflow occurs from multiplication or addition of the mantissa, shift prior to the next addition is inhibited and a bit is added to the exponent result. Each cell comprises a full adder 14 and gates and inverters as shown. The various input and output leads are connected to the corresponding output and input leads of adjacent cells as in Fig. 3, which illustrates a multiplier for numbers with 4-bit mantissas and exponents. The lowermost row of cells receives the multiplicand bits on c and the multiplier mantissa on b. The exponent bits of the multiplier are received on d of the cells h11, h21, h31, h41 corresponding to the multiplicand exponent. In the case of the mantissa cells, a O-bit is applied to d, i and j of the bottom row. As a result the bits on c and b are added, the bit on c is passed via k to the diagonally adjacent row, and the carry bit (if any) passed via g to e of the next cell. Multiplication proceeds by addition and shift from row to row. If overflow occurs, i.e. if a bit appears on g or k of the rightmost cells of any row except topmost, a 1-bit is applied to j of the next row, the carry bit on g is applied to p, and the bit on k to n. As a result of the 1-bit on j, in the remaining mantissa cells the bit on c is passed via l to n of the vertically adjacent cell, and the sub-total bit from d via m to p of the horizontally adjacent cell. In other words, there is no shift prior to the next addition, contrary to the operation when there is no overflow. In the case of the exponent cells, a 1-bit is applied to i, so that the adders in the first row add the relevant bits of the portions of the exponents. The sum output f is applied to d of the next row. There is a 0-bit on k since gate 30 is inhibited by i. When a 1-bit appears on j due to overflow from the mantissa section c is passed to n of the vertically adjacent cell and d to p of the horizontally adjacent cell, as before, and a 1- bit is added to the left-most cell of the relevant row since j is connected to e in this cell, so increasing the exponent portion by 1. Rounding up may be performed by connecting f and i of the topmost row to additional cells, Fig. 7 (not shown), and setting aside one row and column of the array. The set aside row serves to add 1 to the exponent if there is a carry from the last stage of the preceding row. The additional cells then provide the mantissa of the result of the multiplication rounded up in accordance with the least significant bit. Multiplication of negative numbers or of numbers with the mantissa or exponent in 2’s complement form is referred to. The array may perform as an adder if a 1-bit is applied to all inputs i.
GB5112271A
1971-11-03
1971-11-03
Binary arithmetic units
Expired
GB1414958A
(en)
Priority Applications (1)
Application Number
Priority Date
Filing Date
Title
GB5112271A
GB1414958A
(en)
1971-11-03
1971-11-03
Binary arithmetic units
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
GB5112271A
GB1414958A
(en)
1971-11-03
1971-11-03
Binary arithmetic units
Publications (1)
Publication Number
Publication Date
GB1414958A
true
GB1414958A
(en)
1975-11-19
Family
ID=10458745
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB5112271A
Expired
GB1414958A
(en)
1971-11-03
1971-11-03
Binary arithmetic units
Country Status (1)
Country
Link
GB
(1)
GB1414958A
(en)
1971
1971-11-03
GB
GB5112271A
patent/GB1414958A/en
not_active
Expired
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Legal Events
Date
Code
Title
Description
1976-03-31
PS
Patent sealed
1982-08-25
PCNP
Patent ceased through non-payment of renewal fee
