GB1420787A – Electronic binary checking circuit injectable preparations
– Google Patents
GB1420787A – Electronic binary checking circuit injectable preparations
– Google Patents
Electronic binary checking circuit injectable preparations
Info
Publication number
GB1420787A
GB1420787A
GB2162773A
GB2162773A
GB1420787A
GB 1420787 A
GB1420787 A
GB 1420787A
GB 2162773 A
GB2162773 A
GB 2162773A
GB 2162773 A
GB2162773 A
GB 2162773A
GB 1420787 A
GB1420787 A
GB 1420787A
Authority
GB
United Kingdom
Prior art keywords
inputs
gate
circuit
input
gates
Prior art date
1972-06-20
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2162773A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1972-06-20
Filing date
1973-05-07
Publication date
1976-01-14
1973-05-07
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp
1976-01-14
Publication of GB1420787A
publication
Critical
patent/GB1420787A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
238000002360
preparation method
Methods
0.000
title
1
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F11/00—Error detection; Error correction; Monitoring
G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes
H—ELECTRICITY
H03—ELECTRONIC CIRCUITRY
H03K—PULSE TECHNIQUE
H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K19/007—Fail-safe circuits
H03K19/0075—Fail-safe circuits by using two redundant chains
Abstract
1420787 Checking input codes INTERNATIONAL BUSINESS MACHINES CORP 7 May 1973 [20 June 1972] 21627/73 Heading G4H A binary code for checking that at least k out of n binary input variables are 1 comprises a circuit which is representable by the equation (c k,n ,d k,n ) = (a n e k,n-1 (a 1 ,a 2 , … a n-1 ),a n e k-1,n-1 (a 1 , a 2 … a n-1 )), where a 1 … a n are the input variables, e k,n is an OR circuit receiving outputs from AND circuits, each of the AND circuits receiving k of the input variables, and wherein (c k,n , d k,n ) = (0, 1) or (1, 0) when at least k of the n inputs are 1, and (0, 0) otherwise. The terms c k,n and d k,n may be represented further as c k,n = a n Àa 1 Àa 2 Àa 3 … a k va n Àa 1 Àa 2 … a k-1 Àa k+1 v … va n Àa n-k … a n-1 and, d k,n = a n Àa 1 Àa 2 … a k-1 va n Àa 1 Àa 2 … a k-2 Àa k v … va n Àa n-k+1 …a n-1 where «v» represents an OR function. As shown in Fig. 1, the arrangement when n = 4; k = 2 comprises AND gates 101-105 each receiving 2 of the inputs together with a 4 and supplying outputs to OR gate 113, the output 114 of which is c k,n . Similarly, the inputs are taken to AND gates 107-111, a 4 to each gate and the other inputs singly to respective gates. The output 116 of OR gate 115 is d k,n . A further circuit, Fig. 4, is adapted to provide a similar 2-bit output indicative that less than or equal to i of n binary inputs is equal to 1, in this event where n = 4, i = 3. As shown 3 OR gates 119- 123 receive a respective one of 3 of the inputs and the inverted 4th input. Their outputs are coupled to an AND gate 127 and the 2-bit word 13 composed of the 4th input non-inverted, and the output 126 of gate 127. The equations of this circuit for the general case are provided in the Specification. These two types of circuit may be combined, Fig. 8 (not shown) to provide a 2-bit word indicative of whether the number of l’s in an input set is greater than or equal to k and less than or equal to i.
GB2162773A
1972-06-20
1973-05-07
Electronic binary checking circuit injectable preparations
Expired
GB1420787A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US26469372A
1972-06-20
1972-06-20
Publications (1)
Publication Number
Publication Date
GB1420787A
true
GB1420787A
(en)
1976-01-14
Family
ID=23007201
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB2162773A
Expired
GB1420787A
(en)
1972-06-20
1973-05-07
Electronic binary checking circuit injectable preparations
Country Status (9)
Country
Link
US
(1)
US3784977A
(en)
JP
(2)
JPS5224366B2
(en)
BR
(1)
BR7304557D0
(en)
CA
(1)
CA992210A
(en)
DD
(1)
DD107155A5
(en)
DE
(1)
DE2327352C3
(en)
FR
(1)
FR2190294A5
(en)
GB
(1)
GB1420787A
(en)
IT
(1)
IT987429B
(en)
Families Citing this family (5)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3901861A
(en)
*
1973-11-07
1975-08-26
Uniroyal Inc
Molecular weight jumping of elastomeric polymers
US3886520A
(en)
*
1974-04-03
1975-05-27
Sperry Rand Corp
Checking circuit for a 1-out-of-n decoder
JPS60107582U
(en)
*
1983-12-23
1985-07-22
松下電工株式会社
assembly frame
US5179561A
(en)
*
1988-08-16
1993-01-12
Ntt Data Communications Systems Corporation
Totally self-checking checker
US6496790B1
(en)
*
2000-09-29
2002-12-17
Intel Corporation
Management of sensors in computer systems
Family Cites Families (1)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US3559167A
(en)
*
1968-07-25
1971-01-26
Ibm
Self-checking error checker for two-rail coded data
1972
1972-06-20
US
US00264693A
patent/US3784977A/en
not_active
Expired – Lifetime
1973
1973-05-04
CA
CA170,775A
patent/CA992210A/en
not_active
Expired
1973-05-07
GB
GB2162773A
patent/GB1420787A/en
not_active
Expired
1973-05-15
IT
IT24077/73A
patent/IT987429B/en
active
1973-05-18
JP
JP48054852A
patent/JPS5224366B2/ja
not_active
Expired
1973-05-25
FR
FR7321358*A
patent/FR2190294A5/fr
not_active
Expired
1973-05-29
DE
DE2327352A
patent/DE2327352C3/en
not_active
Expired
1973-06-18
DD
DD171624A
patent/DD107155A5/xx
unknown
1973-06-19
BR
BR4557/73A
patent/BR7304557D0/en
unknown
1975
1975-06-24
JP
JP7713275A
patent/JPS571019B2/ja
not_active
Expired
Also Published As
Publication number
Publication date
IT987429B
(en)
1975-02-20
US3784977A
(en)
1974-01-08
JPS4944643A
(en)
1974-04-26
BR7304557D0
(en)
1974-08-22
CA992210A
(en)
1976-06-29
DE2327352B2
(en)
1975-04-10
DD107155A5
(en)
1974-07-12
JPS5224366B2
(en)
1977-06-30
DE2327352A1
(en)
1974-01-10
FR2190294A5
(en)
1974-01-25
JPS571019B2
(en)
1982-01-08
DE2327352C3
(en)
1975-12-11
JPS5118444A
(en)
1976-02-14
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Legal Events
Date
Code
Title
Description
1976-05-26
PS
Patent sealed [section 19, patents act 1949]
1983-12-21
PCNP
Patent ceased through non-payment of renewal fee
