GB1447297A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1447297A – Data processing system
– Google Patents

GB1447297A – Data processing system
– Google Patents
Data processing system

Info

Publication number
GB1447297A

GB1447297A
GB5352173A
GB5352173A
GB1447297A
GB 1447297 A
GB1447297 A
GB 1447297A
GB 5352173 A
GB5352173 A
GB 5352173A
GB 5352173 A
GB5352173 A
GB 5352173A
GB 1447297 A
GB1447297 A
GB 1447297A
Authority
GB
United Kingdom
Prior art keywords
channel
address
store
logic
data
Prior art date
1972-12-06
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB5352173A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Ltd

Fujitsu IT Holdings Inc

Original Assignee
Fujitsu Ltd
Amdahl Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1972-12-06
Filing date
1973-11-19
Publication date
1976-08-25

1973-11-19
Application filed by Fujitsu Ltd, Amdahl Corp
filed
Critical
Fujitsu Ltd

1976-08-25
Publication of GB1447297A
publication
Critical
patent/GB1447297A/en

Status
Expired
legal-status
Critical
Current

Links

Espacenet

Global Dossier

Discuss

Classifications

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F13/10—Program control for peripheral devices

G—PHYSICS

G06—COMPUTING; CALCULATING OR COUNTING

G06F—ELECTRIC DIGITAL DATA PROCESSING

G06F12/00—Accessing, addressing or allocating within memory systems or architectures

G06F12/02—Addressing or allocation; Relocation

G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

G06F12/10—Address translation

G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Abstract

1447297 Data processing AMDAHL CORP and FUJITSU Ltd 19 Nov 1973 [6 Dec 1972] 53521/73 Heading G4A A multichannel data processing unit comprises a main store, instruction unit, execution unit, input/output control and logic circuitry for converting virtual addresses contained in instruction words into real addresses using for each channel an associated stored address conversion parameter. The input/output control comprises a channel unit which can transfer data between storage control and a channel memory (448, Fig. 2, not shown) in the channel unit under the control of a logic unit (4301) and transfer information between the channel memory and the input/output devices under the control of a logic unit (4321). As described the logic units are part of a shift register in a channel memory, the memory also comprising a local channel store 406 (Fig. 3) including a channel buffer store and a subchannel state store and a sub-channel buffer store 408. Registers 404 are operative to store data or write data into the storage unit at an address held in a store unit address register (464, Fig. 4, not shown). Data to be fed to the input/ output devices by interface logic 407 is held in a register (468) and data for the devices entered into a further register (438). Assuming initially that all the channels being controlled are idle when the first input/output command is fetched by the instruction unit, the effective address is fed via bus 426 to the channel unit. State logic 428 recognizes the instruction as a start input/output instruction and waits for the channel information which is circulating through the shift register to arrive in location SCS1 when operation and control logic 429 allows the contents of stage SCS1 to be entered into a staging register (721, Fig. 6, not shown) and stage SCS2 is latched in the operation pending condition. Logic 429 becomes dedicated to the address channel (other sections of the shift register may be dedicated to other channels) and fetches a channel address word into the channel buffer store in the local store 406. Procedure logic locates the address of the first channel command word. If the first command is a transfer of data to main store, logic 432 causes data to be transferred from input/output controller 411 via interface 407 to the local channel store 406. Logic 430 controls the transfer to main store when sufficient data has been received. Operations may be effected with either real or virtual addresses, controlled by command words TL or TVL. When a command TVL is issued (designated by code XX010000 in bits 0-7) bits 8-31 designate the next logical address. The second part of the command word represent a sub-channel translation word STW in which the first 8 bits specify the segment table length in units of 64 bytes, the next 16 bits specify the starting address of the segment table, 2 bits specify the page size and 2 bits specify the segment size. Translation is effected within the storage unit 4 (Fig. 7). The first part of the first channel command word results in the channel number on bus 426 (Fig. 3) being used to address local channel store 406 to cause data on bus 419 to be stored in the channel buffer store. The sub-channel translation word STW is latched into register 326 (Fig. 7). The logical address in the command word is fed on bus 353 to translation adder 327 for addition to the segment field of the word STW. The result on bus 397 is fed to buffer address register 363 to access buffer store 355 to read out the real starting address to register 390, this being then fed to the translation adder together with the page field to derive a further address for buffer 355 which results in a real address being fed to the register 390 for concatenation with the low order bits of the channel command word. The real address is then stored in the channel buffer store of the local channel store 406. Checks are made after each operation to ensure that the fields of the segment and page are not longer than the size of the page table and the segment table. When a TL command is issued designated by code XX100000 in bits 0-7, bits 8-31 specify the real address of the next command. An indirect data addressing facility enables mapping between 24 bit virtual addresses.

GB5352173A
1972-12-06
1973-11-19
Data processing system

Expired

GB1447297A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US31273372A

1972-12-06
1972-12-06

Publications (1)

Publication Number
Publication Date

GB1447297A
true

GB1447297A
(en)

1976-08-25

Family
ID=23212764
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB5352173A
Expired

GB1447297A
(en)

1972-12-06
1973-11-19
Data processing system

Country Status (15)

Country
Link

JP
(1)

JPS5610655B2
(en)

AT
(1)

AT351302B
(en)

AU
(1)

AU498489B2
(en)

BE
(1)

BE808257A
(en)

BR
(1)

BR7309515D0
(en)

CA
(1)

CA1008563A
(en)

CH
(1)

CH584427A5
(en)

DE
(1)

DE2360303C2
(en)

ES
(1)

ES421412A1
(en)

FR
(1)

FR2210309A5
(en)

GB
(1)

GB1447297A
(en)

IT
(1)

IT1006675B
(en)

NL
(1)

NL7316646A
(en)

NO
(1)

NO141450C
(en)

SE
(1)

SE402495B
(en)

Cited By (3)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

US4403282A
(en)

1978-01-23
1983-09-06
Data General Corporation
Data processing system using a high speed data channel for providing direct memory access for block data transfers

WO1998006039A1
(en)

1996-08-07
1998-02-12
Sun Microsystems, Inc.
Disambiguation memory circuit and operating method

WO1998006038A1
(en)

1996-08-07
1998-02-12
Sun Microsystems, Inc.
Architectural support for software pipelining of loops

Families Citing this family (18)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

NL7416631A
(en)

1974-12-20
1976-06-22
Philips Nv

CALCULATOR SYSTEM.

US3990051A
(en)

1975-03-26
1976-11-02
Honeywell Information Systems, Inc.
Memory steering in a data processing system

JPS5922977B2
(en)

1975-06-30
1984-05-30
ハネイウエル・インフオメ−シヨン・システムスインコ−ポレ−テツド

Page memory recall method using input/output device

JPS5325326A
(en)

1976-06-07
1978-03-09
Amdahl Corp
Data processing system with plural channel processor

JPS533029A
(en)