GB1462150A – Stored programme controlled telecommunication system
– Google Patents
GB1462150A – Stored programme controlled telecommunication system
– Google Patents
Stored programme controlled telecommunication system
Info
Publication number
GB1462150A
GB1462150A
GB2351475A
GB2351475A
GB1462150A
GB 1462150 A
GB1462150 A
GB 1462150A
GB 2351475 A
GB2351475 A
GB 2351475A
GB 2351475 A
GB2351475 A
GB 2351475A
GB 1462150 A
GB1462150 A
GB 1462150A
Authority
GB
United Kingdom
Prior art keywords
register
phase
during
iar
logic
Prior art date
1974-06-06
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2351475A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1974-06-06
Filing date
1975-05-29
Publication date
1977-01-19
1975-05-29
Application filed by Telefonaktiebolaget LM Ericsson AB
filed
Critical
Telefonaktiebolaget LM Ericsson AB
1977-01-19
Publication of GB1462150A
publication
Critical
patent/GB1462150A/en
Status
Expired
legal-status
Critical
Current
Links
Espacenet
Global Dossier
Discuss
Classifications
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F9/00—Arrangements for program control, e.g. control units
G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F9/22—Microcontrol or microprogram arrangements
G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
G—PHYSICS
G06—COMPUTING; CALCULATING OR COUNTING
G06F—ELECTRIC DIGITAL DATA PROCESSING
G06F9/00—Arrangements for program control, e.g. control units
G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F9/22—Microcontrol or microprogram arrangements
G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
H—ELECTRICITY
H04—ELECTRIC COMMUNICATION TECHNIQUE
H04Q—SELECTING
H04Q3/00—Selecting arrangements
H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
Abstract
1462150 Automatic exchange systems TELEFONAKTIEBOLAGET L M ERICSSON 29 May 1975 [6 June 1974] 23514/75 Heading H4K In an SPC exchange, operation of and condition-testing of telecommunications components is effected with a microprocessor type interface which steps through a programme sequence in a manner dependent on a start instruction, each step comprising three time phases during which only prescribed actions may take place and a phase being lengthened so as to prolong the step until a certain result is achieved. An exchange EX (Fig. 1) has a plurality of addressable operating points OP, e.g. bi-stable circuits that serve as relay drivers, a plurality of test points TP, e.g. flip-flops that have a «0» or «1» state in dependence upon an open or closed line loop condition, and a plurality of registers Rl, R2 containing, for example, a binary word indicative of the condition of a set of crosspoints. All the above components are linked by a data bus DB to the interface which comprises instruction registers IR, an addressing arrangement ASG and a three-phase clock pulse generator PG. In operation, an initial address register IAR is filled with a code indicative of where a programme sequence should begin. This code is effective to start the generator PG whereby during the first phase #1 of a processing cycle, the code is decoded by the addressing arrangement ASG (logic L1) in order to access a particular register (usually an instruction register IR). During phase #2, an address a is read out of the accessed IR register, decoded in ASG and used over line as to address a particular operating or test point or to read-out a particular data register R1, R2. During subsequent cycles, in phases #2, #3, data may be transferred from one register to another (logic L3). In the cases where an operate (or test) function is required, the successful completion of the function will be denoted by a change of state of a test point associated with the operating point, such successful conclusion being indicated through logic L4 during the final phase #3 of a cycle. Many functions require a plurality of steps to achieve satisfactory completion. This is achieved by incrementing the initial address in IAR by one during each processing cycle (logic L2 or L4) so that a further instruction register IR may be accessed in the following cycle. When the function is complete, the phase generator PG is turned off and the system is zeroized. In a path finding arrangement (Fig. 2), registers R4, R5 contain the free/busy conditions at the inlet and outlet stages of a network. Useable paths are denoted by coincidence of «1» marks in these two registers (AND gate G3). A demand for path finding is inserted by a marker into register SR. This mark is used via gates G6, G7 to start the phase generator PG and via logic L3 is written into the initial address register IAR. The instruction registers, in this case, are formed as a read-only memory ROM which is first accessed during phase #1 (gate G2) of the first processing cycle by the mark in IAR. The steps of the process are then run-through during successive cycles by incrementing the mark in IAR thereby accessing different cells in ROM. The cells contain relevant address and operate instructions for the seven different steps of the process. (An eighth step permits branching to another instruction in the event that no free path is available.) These consist essentially in gaining access to particular register R4, R5; transferring their ANDed contents to SHR; checking that SHR has at least one «1» bit; stepping SHR to find the first «1» bit (this entails holding the same phase in a same cycle, gate L5); and then conveying the addresses of the inlet and outlet crosspoints corresponding to the selected path to the buffers. A next, but different function, would be to use these addresses to set-up the path.
GB2351475A
1974-06-06
1975-05-29
Stored programme controlled telecommunication system
Expired
GB1462150A
(en)
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
SE7407431A
SE376354B
(en)
1974-06-06
1974-06-06
Publications (1)
Publication Number
Publication Date
GB1462150A
true
GB1462150A
(en)
1977-01-19
Family
ID=20321339
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
GB2351475A
Expired
GB1462150A
(en)
1974-06-06
1975-05-29
Stored programme controlled telecommunication system
Country Status (19)
Country
Link
US
(1)
US4002851A
(en)
JP
(1)
JPS5818836B2
(en)
AU
(1)
AU497191B2
(en)
BE
(1)
BE829976A
(en)
BR
(1)
BR7503523A
(en)
CA
(1)
CA1052463A
(en)
DK
(1)
DK138298B
(en)
EG
(1)
EG13379A
(en)
ES
(1)
ES438259A1
(en)
FI
(1)
FI58418C
(en)
FR
(1)
FR2274190A1
(en)
GB
(1)
GB1462150A
(en)
HU
(1)
HU171888B
(en)
IN
(1)
IN142560B
(en)
MY
(1)
MY7800103A
(en)
NL
(1)
NL7506750A
(en)
NO
(1)
NO137803C
(en)
SE
(1)
SE376354B
(en)
YU
(1)
YU36091B
(en)
Families Citing this family (5)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US4487630A
(en)
*
1982-10-25
1984-12-11
Cabot Corporation
Wear-resistant stainless steel
JPS6130454A
(en)
*
1984-07-21
1986-02-12
Motoyasu Tanaka
Environment improving method for living space of automobile
US5471526A
(en)
*
1994-02-28
1995-11-28
Telefonaktiebolaget L M Ericsson (Publ.)
Tracing with keys and locks on a telecommunication network
US20060020413A1
(en)
*
2004-07-26
2006-01-26
Septon Daven W
Methods and apparatus for providing automated test equipment with a means to jump and return in a test program
CN113254079B
(en)
*
2021-06-28
2021-10-01
广东省新一代通信与网络创新研究院
Method and system for realizing self-increment instruction
Family Cites Families (2)
* Cited by examiner, † Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
FR1603447A
(en)
*
1968-08-08
1971-04-19
US3825693A
(en)
*
1972-09-25
1974-07-23
Tele Resources Inc
Time division multiplex branch exchange
1974
1974-06-06
SE
SE7407431A
patent/SE376354B/xx
not_active
IP Right Cessation
1975
1975-05-19
US
US05/578,734
patent/US4002851A/en
not_active
Expired – Lifetime
1975-05-21
IN
IN1027/CAL/1975A
patent/IN142560B/en
unknown
1975-05-28
FI
FI751555A
patent/FI58418C/en
not_active
IP Right Cessation
1975-05-29
AU
AU81685/75A
patent/AU497191B2/en
not_active
Expired
1975-05-29
GB
GB2351475A
patent/GB1462150A/en
not_active
Expired
1975-06-03
HU
HU75EI00000624A
patent/HU171888B/en
unknown
1975-06-04
DK
DK252575AA
patent/DK138298B/en
unknown
1975-06-04
BR
BR4512/75D
patent/BR7503523A/en
unknown
1975-06-04
YU
YU1440/75A
patent/YU36091B/en
unknown
1975-06-05
ES
ES438259A
patent/ES438259A1/en
not_active
Expired
1975-06-05
JP
JP50068137A
patent/JPS5818836B2/en
not_active
Expired
1975-06-05
NO
NO751996A
patent/NO137803C/en
unknown
1975-06-05
FR
FR7517658A
patent/FR2274190A1/en
active
Granted
1975-06-06
BE
BE157120A
patent/BE829976A/en
not_active
IP Right Cessation
1975-06-06
NL
NL7506750A
patent/NL7506750A/en
not_active
Application Discontinuation
1975-06-06
CA
CA228,756A
patent/CA1052463A/en
not_active
Expired
1975-06-07
EG
EG329/75A
patent/EG13379A/en
active
1978
1978-12-30
MY
MY103/78A
patent/MY7800103A/en
unknown
Also Published As
Publication number
Publication date
FR2274190A1
(en)
1976-01-02
NO137803B
(en)
1978-01-16
CA1052463A
(en)
1979-04-10
MY7800103A
(en)
1978-12-31
DK252575A
(en)
1975-12-07
YU144075A
(en)
1981-02-28
EG13379A
(en)
1981-03-31
DK138298B
(en)
1978-08-07
FI58418C
(en)
1981-01-12
ES438259A1
(en)
1977-04-16
JPS5818836B2
(en)
1983-04-14
BR7503523A
(en)
1976-05-25
AU8168575A
(en)
1976-12-02
SE376354B
(en)
1975-05-12
FI751555A
(en)
1975-12-07
YU36091B
(en)
1981-11-13
AU497191B2
(en)
1978-12-07
NL7506750A
(en)
1975-12-09
DK138298C
(en)
1979-01-22
FR2274190B1
(en)
1979-03-23
BE829976A
(en)
1975-10-01
US4002851A
(en)
1977-01-11
FI58418B
(en)
1980-09-30
IN142560B
(en)
1977-07-30
JPS518808A
(en)
1976-01-24
NO751996L
(en)
1975-12-09
HU171888B
(en)
1978-04-28
NO137803C
(en)
1978-05-10
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Legal Events
Date
Code
Title
Description
1977-06-01
PS
Patent sealed [section 19, patents act 1949]
1987-01-21
PCNP
Patent ceased through non-payment of renewal fee
