GB1577806A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1577806A – Digital-to-analogue converter
– Google Patents

GB1577806A – Digital-to-analogue converter
– Google Patents
Digital-to-analogue converter

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Publication number
GB1577806A

GB1577806A
GB36783/77A
GB3678377A
GB1577806A
GB 1577806 A
GB1577806 A
GB 1577806A
GB 36783/77 A
GB36783/77 A
GB 36783/77A
GB 3678377 A
GB3678377 A
GB 3678377A
GB 1577806 A
GB1577806 A
GB 1577806A
Authority
GB
United Kingdom
Prior art keywords
charge
output
input
potential well
potential
Prior art date
1976-10-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB36783/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-10-29
Filing date
1977-09-02
Publication date
1980-10-29

1977-09-02
Application filed by International Business Machines Corp
filed
Critical
International Business Machines Corp

1980-10-29
Publication of GB1577806A
publication
Critical
patent/GB1577806A/en

Status
Expired
legal-status
Critical
Current

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239000000758
substrate
Substances

0.000
claims
description
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230000005669
field effect
Effects

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claims
description
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239000004065
semiconductor
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description
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impurity
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claims
description
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chemical substances by application
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discharging
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dependent effect
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nuclear magnetic resonance pulse sequence
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claims
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diffusion process
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description
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diagram
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description
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chemical reaction
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method
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potential barrier
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barrier function
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coupling
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coupling process
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coupling reaction
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decreasing effect
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Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched

H01L29/76—Unipolar devices, e.g. field effect transistors

H01L29/762—Charge transfer devices

H01L29/765—Charge-coupled devices

H01L29/768—Charge-coupled devices with field effect produced by an insulated gate

H01L29/76833—Buried channel CCD

H—ELECTRICITY

H03—ELECTRONIC CIRCUITRY

H03M—CODING; DECODING; CODE CONVERSION IN GENERAL

H03M1/00—Analogue/digital conversion; Digital/analogue conversion

H03M1/66—Digital/analogue converters

H03M1/74—Simultaneous conversion

H03M1/80—Simultaneous conversion using weighted impedances

H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices

H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Description

PATENT SPECIFICATION
( 11) ( 21) Application No 36783/77 ( 22) Filed 2 Sept 1977 ( 19) ( 31) Convention Application No 736 970 ( 32) Filed 29 Oct 1976 in ( 33) United States of America (US) ( 44) Complete Specification published 29 Oct 1980 , ( 51) INT CL 3 H 03 K 13/02 H Ol L 29/78 ( 52) Index at acceptance H 3 H 13 D 3 C 3 G 6 B 6 D 7 B 7 F 8 B BD H 1 K ICA l CC 9 4 C 11 4 C 14 4 C 14 A 9 D 1 9 R 2 CCX ( 72) Inventor BARRY JAY RUBIN ( 54) DIGITAL-TO-ANALOGUE CONVERTER ( 71) We, INTERNAT Io NAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following
statement: –
The invention relates to digital-to-analogue converters.
As is well understood, serial digital-toanalogue conversion can be accomplished with the aid of charge storage devices and programmed switching means for selectively coupling the charge storage devices together, More particularly, the programming is so arranged that a fixed input charge (representing a binary 1 or 0) is summed with a pre-existing stored input charge (if any), the combined charges are split in half and one of the split halves is summed with the next input charge, etc, until input charges corresponding to all input serial binary bits have been so processed The resulting charge in the charge splitter represents the analogue value of the serial binary input Such a technique is described in the book «Electronic Analogue/Digital Conversations» by Hermann Schmid, Van Nostrand Rhinehold Company, 1970, pages 186 and 187.
The invention provides a charge coupled device capable of serially converting a multibit digital input into an analogue output, said device comprising a semiconductor substrate; an insulating layer on a surface of the substrate; input means, responsive to the current bit of the digital input, for establishing a first predetermined quantity of charge in a first potential well zone underlying a first charge electrode formed on the insulating layer when the bit has one value and a second predetermined quantity of charge when the bit has the other value; second and third potential well zones underlying spaced second and third charge electrodes formed on the insulating layer; output means for receiving charge from the third potential well zone and for providing an output signal dependant on the charge received thereby; first, second and third control electrodes disposed respectively between the first and second charge electrodes, the second and third charge electrodes and the third charge electrode and the output means for controlling the transfer of charge therebetween; and means for providing a predetermined sequence of control signal pulses to the electrodes so that during the sequence charge established in the first potential well zone by the input means is transferred from the first to the second potential well zone and combined with any charge previously held in the second zone, thereafter the combined charge is divided equally between the second and third potential well zone, and then the half of the combined charge in the third potential well zone is transferred to the output means.
By way of example there is described herein a charge-coupled device forming a serial digital-to-analogue converter and comprising charge source and charge collection diffusions in a semiconductor substrate separated from each other by a series of gate electrodes The gate electrodes are energized by a predetermined pulse waveform sequence, independent of the value of the input digital numbers to be converted The gate electrodes provide charge storage and charge splitting wells in the substrate in response to applied potentials In operation, a fixed input charge (representing a binary 1 or 0) is summed with a pre-existing stored input charge (if any), the combined charges are split in half and one of the split charge halves is summed with the next input charge, etc, until input charges corresponding to all input binary bits have been sequentially processed The other split charge half in the charge splitter is outputted through the charge collecting diffusion and represents the analogue value of the binary input.
The invention will now be further de1 577 806 2 1,577,806 2 scribed by way of example, with reference to the accompanying drawings, in which:Figure 1 is a simplified cross-sectional view of a preferred embodiment of a chargecoupled device forming a digital-to-analogue converter embodying the invention; Figures 2 A, 2 B, 2 C and 2 D are a series of diagrams representing the control voltages and the resulting potential wells in the converter of Figure 1 at respective times; and Figure 3 is a plan view of a device in which the convertor as well as the schematically represented field effect transistors of
Figure 1 are including in one integrated circuit.
Buried channel charge-coupled devices are used to input, split, transfer and output the charge in the preferred embodiment of Figure 1 The buried channel structure provides for high fringing fields which increase the speed of operation of the digital-to-analogue converter Alternatively, a surface chargecoupled device structure (having no N diffusion 1) also is suitable for use with the present invention.
N (buried channel) diffusion 1 is made in P substrate 2 Input N+ diffusion 3 and output N+ diffusion 4 are made into substrate 2 at opposite ends of diffusion 1 A voltage waveform, representing the serial bits of an input digital number (least significant bit first) which is to be converted to a corresponding analog value, is applied via line 5 to N+ diffusion 3 In the example to be described, an input voltage of 15 volts represents the binary value 0 whereas an input voltage of 8 volts represents the binary value 1 Charge is injected from N+ diffusion 3 when the input voltage waveform is at 8 volts The injected charge travels from input diffusion 3 to output diffusion 4 under the control of a predetermined sequence of control voltage pulses which are applied to respective insulated gate electrodes located along the path of charge travel The charge received by diffusion 4 determines the conductivity of output FET 16 The gate electrodes comprise electrodes 6 to 12, inclusive, each of which is insulated from diffused substrate 2 by a thin slicon dioxide layer 13.
Gate electrodes 9 and 11 receive the same control potential via line 14 Each of the other gate electrodes receive respective control potentials.
The control voltages applied to N+ diffusions 3 and 4 and gate electrodes 6 through 12 are represented by the numerals located adjacent the respective «steps» comprising the diagrams of Figures 2 A, 2 B, 2 C and 2 D.
The levels of the «steps» represent the depths of the respective potential wells which are created in the N diffused area 1 as a result of the application of the indicated voltages to the overlying corresponding diffusions 3 and 4 and the gate electrodes 6-12.
The diagram of Figure 2 A represents the amplitudes (plotted negatively) of the potential well depths which are simultaneously produced at time to by the indicated voltages applied to respective diffusions and gate elec 70 trodes The diagrams of Figures 2 A through 2 D are aligned with the structure of Figure 1 so that the value of each indicated voltage represents the voltage applied to the diffusion or gate electrode, as the case may be, aligned 75 directly above Thus, at time to, the voltages applied to diffusion 3, gates 6, 7, 8, 9, 10, 11 and 12 and output diffusion 4 are 8, 5, 10, 0, 15, 0, 15, 0 and 17 volts, respectively.
It should be noted that the use of the 80 buried channel N layer 1 results in potential well depth greater than the voltage applied to the overlying gate electrode On the other hand, the potential well depth of a diffused area such as area 3 is equal to the 85 voltage applied to said area.
FET 15 is used to reset and then isolate the N+ output diffusion 4 A source follower comprising the output FET 16 and a series connected FET 17 is used as an output 90 buffer Transistors 15 16 and 17 preferably mav be integrated with the basic structure of the buried channel dipfital-to-analog converter as will be described later in connection with the embodiment shown in Figure 3 95 As is well understood, serial diaital-toanalog conversions can be accomnlished by appronrintelv summing a stored charge with an input charge, dividing the resulting charge in half and then summing the divided charge 100 with the next following input charge, etc.
The first input charge represents the least significant bit of the input number to be converted Such conversion is accomplished by the preferred embodiment of the present 105 invention represented in Figure 1 upon application thereto of the voltages indicated represented by the diagrams of Figures 2 A through 2 D at the respective times to through t:, As an aid in understanding the operation 110 of the preferred embodiment, the diagrams of Fioures 2 A throuph 2 D have been plotted negatively, i e, the upper portions of each diarram representing the less positive voltages and the lower portions of each diagram 115 representing the more positive voltages The adonted convention permits each voltage dinaram also to be interpreted as a diagram of the potential wells created within diffused substrate 2 in response to the voltages ap 120 plied to the respective diffusions and gate electrodes of Figure 1.
Referring to the t, diarram of Firure 2 A, with 8, 5 and 10 volts applied to N+ diffusion 3, and gate electrodes 6 and 7, respectively, 125 a charge is inputted (representing the binary value 1) to fill the potential wells underneath gate electrodes 6 and 7 of Figure 1 to a level represented by the dashed line 28 of Figure 2 A The input charge is trapped by the po 130 1,577,806 1,577,806 tential barrier underneath gate electrode 8 corresponding to a 0 voltage respectively applied thereto To illustrate the general case wherein previous input charges have accumulated within the charge splitting wells underneath gate electrodes 9 and 11, such charges are represented by the shaded areas designated «Q» in each of the charge splitting wells The charges within the wells are trapped by the potential barriers underneath gate electrodes 8 and 12 and are separated from each other by the potential barrier underneath gate 10, said gates receiving the applied potential of 0 volts.
At time t 1, the voltage applied to charge source diffusion 3 is reset to 15 volts allowing the excess charge represented by dashed line 28 of Figure 2 A to drain off leaving a standard pre-measured charge «Q 01 » in the input storage potential well underneath electrode 7 At the same time, the voltage applied to gates 9 and 11 is reduced to 7 volts and the voltage applied to output gate 12 is increased to 8 volts The result is that the charge Q in the charge splitting well underneath gate 11 is released and driven toward output N+ diffusion 4 (at 17 volts) where it is collected The N+ diffusion potential is decreased by an amount equal to Q where Q is the collected charge and C is C the total output capacitance encountered by the charge The sensed charge represents the analog value of all previously inputted serial digits prior to the digit producing charge «Q,» shown underneath electrode 7 in the diagram of Figure 2 B. At time interval t 2, the voltage of gate 8 is increased to 12 volts, allowing the charge «Q Jn» to be summed with the preexisting charge «Q» in the charge splitting well underneath gate 9.
The resulting charge «Q+Q Jn» is distributed equally between the charge splitting wells underneath the gate electrodes 9 and 11 at time t, by increasing the voltage applied to gate 10 to 16 volts At the same time, the voltage output N+ diffusion 4 is reset to 17 volts by turning on the gate of FET 15 which receives the same voltage as gate 10.
This action completes one cycle of processing an input charge representing a respective serial bit of the input digital number Upon the occurrence of the next succeeding input bit, the digram of Figure 2 A again applies except that the charge sum 1 (Q+Q 1 n) of Figure 2 D is initially stored in each potential well underneath gates 9 and 11 Input diffusion 3 is raised to 8 volts if the next succeeding input binary bit also is a » 1 » If the next succeeding bit is a » O «, source diffusion 3 remains at 15 volts and no charge is caused to flow into the potential wells underneath gates 6 and 7 It should be noted that the voltages discussed in connection with the diagrams of Figures 2 A through 2 D are illustrative only in that actuai operating voltages depend upon the vertical geometry of the device represented in Figure 1, as is well 70 understood in the art.
Figure 3 is a plan view of an integrated circuit device embodying all of the structure shown in Figure 1 including transistors 15, 16 and 17 The structural elements of Figure 75 3 corresponding to those shown in Figure 1 are designated by the same numbers Output N+ diffusion 4, in the integrated structure of Figure 3, also serves as the source of FET 15 whose structure is completed by gate 18 and 80 drain 19 The N+ diffusion 19 serving as the drain of FET 15 also serves as the drain of FET 16 The source of FET 16 and the drain of FET 17 are formed by N+ diffusion 20.
N+ diffusion 21 forms the grounded N+ 85 source of FET 17 Gates 22 and 23 complete the structure of integrated FET’s 16 and 17, respectively.
It should be noted that charge splitting gates 9 and 11 are conductively connected 90 together in the preferred embodiment to receive the same potential at all times Additionally, the voltages on the gates immediately adjacent the splitting gates, i e, gates 8 and 12, also are equal during the charge 95 splitting interval to Consequently, the fringing fields are made sustantially identical with the result that the charge splitting potential wells are substantially identical for maximum charge splitting accuracy Inas 100 much as the accuracy of the overall binaryto-analogue conversion heavily depends upon the accuracy with which the charge splitting is accomplished, maximum accuracy of conversion is achieved 105 Although areas 1, 3 and 4 are termed diffused areas in the preceding specification, it will be observed by those skilled in the art that they may also be formed by impurity implantation, if desired 110

Claims (9)

WHAT WE CLAIM IS –

1 A charge coupled device capable of serially converting a multi-bit digital input into an analogue output, said device com 115 prising a semiconductor substrate; an insulating layer on a surface of the substrate; input means, responsive to the current bit of the dicital input, for establishing a first predetermined quantity of charge in a first 120 potential well zone undervling a first charce electrode formed on the insulating layer when the bit has one value and a second predetermined quantity of charge when the bit has the other value; second and third 125 potential well zones underlying spaced second and third charge electrodes formed on the insulating layer; output means for receiving charge from the third potential well zone and for providing an output signal 130 1,577,806 dependant on the charge received thereby; first, second and third control electrodes disposed respectively between the first and second charge electrodes, the second and third charge electrodes and the third electrode and the output means for controlling the transfer of charge therebetween; and means for providing a predetermined sequence of control signal pulses to the electrodes so that during the sequence charge established in the first potential well zone by the input means is transferred from the first to the second potential well zone and combined with any charge previously held in the second zone, thereafter the combined charge is divided equally between the second and third potential well zone, and then the half of the combined charge in the third potential well zone is transferred to the output means.

2 A device as claimed in claim 1, in which the input means comprise a first region of conductivity type opposite to the conductivity type of the substrate, means for applying respective first or second potentials to that first region when the current bit has one or the other value, and a fourth potential well zone underlying an input electrode formed on the insulating layer adjacent the first charge electrode.

3 A device as claimed in claim 1 or 2, in which the output means comprise a second region of conductivity type opposite to the conductivity type of the substrate and capable of assumning a potential dependent on the charge transferred thereto and means for discharging the second reuion to reset the potential thereof to predetermined value.

4 A device as claimed in claim 3, in which said discharging means comprise a discharge field effect transistor having its controlled current path connected between a supply voltage terminal and the second region and having its gate electrode connected to receive a gating signal to efect discharge of the second region through the transistor.

A device as claimed in claim 3 or 4, in which the output means comprise an output field effect transistor having its controlled current path connected between output and supply voltage terminals and having its gate electrode connected to the second region so that the conductivity of the output transistor is determined by the potential of the second region.

6 A device as claimed in any one of claims 2 to 5, further comprising a surface zone of conductivity type opposite to that of the substrate, said surface zone being of lesser impurity concentration than the first or second regions and extending between the first and second regions.

7 A device as claimed in any one of claims 1 to 6, in which the control pulse sequence is such that the first, second and third control electrodes all receive control pulses of the same amplitude during one portion of said sequence of control pulses.

8 A charge coupled device substantially as hereinbefore described with reference to and as shown in, Figure 1 or Figures 1 and 3 of the accompanying drawings.

9 A device as claimed in claim 8 when operated substantially as hereinbefore described with reference to and shown in, Figures 2 A, 2 B, 2 C and 2 D of the accompanying drawings.
ALAN J LEWIS, Chartered Patent Agent, Agent for the Applicants.
Printed for Her Majesty’s Stationery Office by Burgess & Son (Abingdon), Ltd -1980.
Published at The Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.

GB36783/77A
1976-10-29
1977-09-02
Digital-to-analogue converter

Expired

GB1577806A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
Title

US05/736,970

US4099175A
(en)

1976-10-29
1976-10-29
Charge-coupled device digital-to-analog converter

Publications (1)

Publication Number
Publication Date

GB1577806A
true

GB1577806A
(en)

1980-10-29

Family
ID=24962078
Family Applications (1)

Application Number
Title
Priority Date
Filing Date

GB36783/77A
Expired

GB1577806A
(en)

1976-10-29
1977-09-02
Digital-to-analogue converter

Country Status (6)

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US
(1)

US4099175A
(en)

JP
(1)

JPS5355948A
(en)

DE
(1)

DE2734942C2
(en)

FR
(1)

FR2369688A1
(en)

GB
(1)

GB1577806A
(en)

IT
(1)

IT1114414B
(en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

FR2474257A1
(en)

1979-12-27
1981-07-24
Thomson Csf

CHARGED TRANSFER VOLTAGE GENERATOR, ENCODER AND ANALOGUE-DIGITAL DECODER HAVING SUCH A GENERATOR

JP2672507B2
(en)

1987-05-21
1997-11-05
株式会社東芝

Charge transfer element

JPS641671U
(en)

1987-06-22
1989-01-06

US5014059A
(en)

1987-07-28
1991-05-07
Tektronix, Inc.
Analog-to-digital converter system

US4906997A
(en)

1987-07-28
1990-03-06
Seckora Michael C
CCD device adapted for changing signal formats

US4967198A
(en)

1988-06-13
1990-10-30
Seckora Michael C
Serial-to-parallel analog CCD GaAs device

JP2669591B2
(en)

1992-10-30
1997-10-29
インターナショナル・ビジネス・マシーンズ・コーポレイション

Data line driver

US5400028A
(en)

1992-10-30
1995-03-21
International Business Machines Corporation
Charge summing digital to analog converter

US5539404A
(en)

1993-02-08
1996-07-23
Yasuo Nagazumi
Digital to analog converter using recursive signal dividing charge coupled devices

DE19518966C1
(en)

1995-05-23
1996-09-19
Lg Semicon Co Ltd
Digital=to=analogue converter using special charge-coupled device

US5729233A
(en)

1995-09-22
1998-03-17
Lg Semicon Co., Ltd.
Analog/digital converter using a charge coupled device with poly-gates relatively sized

Family Cites Families (4)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB1457253A
(en)

1972-12-01
1976-12-01
Mullard Ltd
Semiconductor charge transfer devices

US3930255A
(en)

1974-02-06
1975-12-30
Us Navy
Analog to digital conversion by charge transfer device

US3906488A
(en)

1974-02-14
1975-09-16
Univ California
Reversible analog/digital (digital/analog) converter

US3937985A
(en)

1974-06-05
1976-02-10
Bell Telephone Laboratories, Incorporated
Apparatus and method for regenerating charge

1976

1976-10-29
US
US05/736,970
patent/US4099175A/en
not_active
Expired – Lifetime

1977

1977-08-03
DE
DE2734942A
patent/DE2734942C2/en
not_active
Expired

1977-09-02
GB
GB36783/77A
patent/GB1577806A/en
not_active
Expired

1977-09-20
IT
IT27701/77A
patent/IT1114414B/en
active

1977-09-29
FR
FR7729892A
patent/FR2369688A1/en
active
Granted

1977-10-14
JP
JP12258677A
patent/JPS5355948A/en
active
Granted

Also Published As

Publication number
Publication date

JPS5355948A
(en)

1978-05-20

DE2734942C2
(en)

1986-11-27

US4099175A
(en)

1978-07-04

JPS5635371B2
(en)

1981-08-17

FR2369688A1
(en)

1978-05-26

IT1114414B
(en)

1986-01-27

DE2734942A1
(en)

1978-05-03

FR2369688B1
(en)

1980-06-27

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