GB1584756A - Creación de Inventos y Patentes con Inteligencia Artificial

GB1584756A – Methods of manufacturing devices including a pattern of conductor tracks
– Google Patents

GB1584756A – Methods of manufacturing devices including a pattern of conductor tracks
– Google Patents
Methods of manufacturing devices including a pattern of conductor tracks

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Publication number
GB1584756A

GB1584756A
GB33136/77A
GB3313677A
GB1584756A
GB 1584756 A
GB1584756 A
GB 1584756A
GB 33136/77 A
GB33136/77 A
GB 33136/77A
GB 3313677 A
GB3313677 A
GB 3313677A
GB 1584756 A
GB1584756 A
GB 1584756A
Authority
GB
United Kingdom
Prior art keywords
conductor
pattern
intermediate layer
tracks
level
Prior art date
1976-08-11
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Expired

Application number
GB33136/77A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Koninklijke Philips NV

Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
1976-08-11
Filing date
1977-08-08
Publication date
1981-02-18

1977-08-08
Application filed by Philips Gloeilampenfabrieken NV
filed
Critical
Philips Gloeilampenfabrieken NV

1981-02-18
Publication of GB1584756A
publication
Critical
patent/GB1584756A/en

Status
Expired
legal-status
Critical
Current

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conductor
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manufacturing process
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material
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semiconductor
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PXHVJJICTQNCMI-UHFFFAOYSA-N
Nickel
Chemical compound

[Ni]
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treatment
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nickel
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239000004411
aluminium
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aluminium
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aluminium
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metal
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platinum
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chemical substances by application
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gold
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gold
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gold
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polysorbate
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sputter deposition
Methods

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synthetic resin
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Classifications

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L23/00—Details of semiconductor or other solid state devices

H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body

H01L23/4821—Bridge structure with air gap

H—ELECTRICITY

H01—ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/0001—Technical content checked by a classifier

H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

PATENT SPECIFICATION
= ( 21) Application No 33136/77 ( 2 tl ( 31) Convention Application No.
t: 7608901 C ( 33) = ( 44) in ( 51) ( 52) ( 11) 1 584 756 22) Filed 8 Aug 1977 ( 32) Filed 11 Aug 1976 in Netherlands (NL) Complete Specification published 18 Feb 1981
INT CL 3 H Ol L 21/90 Index at acceptance H 1 K 11 Cl A 11 D 3 li D 3 TIC 3 T 5 3 U 6 A 4 C 11 4 C 3 E 4 C 3 G 4 C 3 S 4 F 11 G 4 F 1 C 4 F 22 D 4 F 26 4 F 8 C HAE ( 54) IMPROVEMENTS IN AND RELATING TO METHODS OF MANUFACTURING DEVICES INCLUDING A PATTERN OF CONDUCTOR TRACKS ( 71) We, N V PHILIPS’ GLOEILAMPENFABRIEKEN, a limited liability Company, organised and established under the laws of the Kingdom of the Netherlands, of Emmasingel 29, Eindhoven, the Netherlands, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to performed, to be particularly described in and by the following statement:
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body having at one of its surfaces a plurality of regions forming a first pattern to which regions there are electrically connected a plurality of conductor tracks forming a second pattern, particularly, but not exclusively to a method of manufacturing a semiconductor device having a semiconductor body which is provided at one of its surfaces with a pattern of conductors comprising a first pattern of conductor tracks which form a lowermost conductor level and a second pattern of conductor tracks which forms an uppermost conductor level which is locally connected electrically to the lowermost conductor level, the levels being isolated electrically from each other at the area of the crossing.
Integrated circuits having multi-layer interconnection patterns, sometimes referred to as multi-layer wirings, are generally known Due to the possibility of crossings, the conductor pattern in multi-layer interconnection systems can be constructed to be much more complex than in a single layer interconnection system in which such crossings are not possible The degree of freedom in designing integrated circuits is thus much larger when using a multi-layer interconnection, which is of importance in particular when the number of circuit elements (transistors, diodes, resistors, and so on) of the integrated circuit is very large.
Such complicated circuits are often referred to in literature by L S I (Large Scale Integration).
In the most conventional construction of multi-layer interconnection systems an insulating layer of, for example, silicon 50 oxide is provided over the surface of the body after providing the conductor pattern of the lowermost conductor level At the areas where during the subsequent process steps the connections are to be effected be 55 tween the various levels, holes are formed in said dielectric layer by means of known photomasking and etching methods The dielectric layer insulates the conductor patterns of the various levels electrically 60 from each other at the area of the crossings.
The thickness of the layer is comparatively large so as to minimize the stray capacitances between the various conductor levels.
A specific value for the thickness is 1 65 micron.
Such a system may have important drawbacks in practice The dielectric which is usually formed by a layer of silicon oxide deposited from the gaseous phase often 70 proves to have small apertures, sometimes referred to by » pin holes » in the literature.
Via said » pin holes » short-circuits may occur between the lowermost conductor level and the uppermost conductor 75 level which is usually formed by depositing from the vapour phase or the gaseous phase particles of a suitable metal, for example Aluminium.
Another important drawback resides in 80 the fact that restrictions can be imposed upon the packing density Since the connections between the various levels are to be effected via contact holes in the comparatively thick oxide layer, the distances 85 between juxtaposed conductor tracks of the uppermost level often have to be made larger than is desired in connection with the packing density of the integrated circuit 90 A further drawback is that a separate photolithographic process is required for providing contact holes in the silicon oxide layer for the connections between the various conductor levels 95 Another method of manufacturing multilayer interconnection systems is described by Lepselter in » Bell Systems Technical 1 584756 Journall» of February 1968, pages 269 to 271 In this method, an intermediate layer of, for example, copper is provided on the body and on the lowermost conductor pattern after the conductor pattern of the lowermost level has been vapour-deposited on the body At the sites where the conductor pattern of the uppermost level is to be connected to the pattern of the lowermost level, apertures are etched in the copper layer via a first mask, after which via a second mask the uppermost conductors are provided electrolytically in the form of a layer of gold The copper layer is then etched away so that gold bridges are formed which are separated from the lowermost conductor level at the area of the crossings by an empty space (air) The piers of the gold bridges are formed by parts of the gold layer at the area of the connections.
In this manner crossing conductors can be obtained without short-circuits between the various conductor levels.
Since the dielectric constant of air (vacuum) is considerably smaller than that of silicon oxide, the stray capacitances of a conductor pattern comprising such bridges are generally comparaticely small In this connection the use of such bridges may provide important advantages also in th& case of a single layer interconnection system in which the conductor pattern should form low stray capacitances with regions of, for example, circuit elements formed in the semiconductor body.
However, the method is comparatively complicated and often requires even more process steps than the described conventional method in that the intermediate layer should successively be subjected to two etching treatments, namely an etching treatment to form holes at the area of the connections, to provide the uppermost conductor pattern and to remove the intermediate layer after providing the uppermost conductor pattern Moreover, it is substantially not possible in this method either to provide the conductor tracks as closely together as is often desired with a view to the packing density in integrated semiconductor circuits.
According to the invention there is provided a method of manufacturing a semiconductor device comprising a semiconductor body having at one of its surfaces a plurality of regions forming a first pattern to which regions there are electrically connected a plurality of conductor tracks forming a second pattern, wherein after providing the first pattern an intermediate layer is provided over the surface, said intermediate layer consisting of a material which is electrically conductive, can be etched selectively with respect to the material of the conductor tracks of the second pattern to be provided, and can form a good adhesion with the first pattern and the material of the conductor tracks of the second pattern to be provided, after which the conductor tracks of the second 70 pattern are provided on the intermediate layer and the intermediate layer is subjected to a selective etching treatment in which the tracks of the second pattern form an etching mask and the intermediate layer 75 is locally removel entirely by underetching of the intermediate layer below the tracks of the second pattern and in which the intermediate layer at least at the area of the connections between the conductor tracks 80 of the second pattern and the regions of the first pattern is removed only partly by underetching below the tracks of the second pattern, at least a part of the second pattern forming a conductive connection between 85 two separated parts of the first pattern and via residual portions of the intermediate layers situated on said two separated parts of the first pattern.
Such a method provides the possibility 90 of forming bridges between separate portions of the first pattern in a simple manner Advantages can be obtained in the case of semiconductor devices having only a single layer interconnection in which the 95 stray capacitances between the conductor tracks of the second pattern forming such a single layer interconnection and the elements in the semiconductor body should be kept low and in which the said regions of 100 the first pattern can be formed, for example, by semiconductor zones of circuit elements.
However, the method is of particular use in the case of multi-layer interconnections having crossings between the various con 105 ductor levels.
In accordance with a further aspect of the invention there is provided a method of manufacturing a semiconductor device having a semiconductor body which is pro 110 vided at one of its surfaces with a conductor pattern comprising a first pattern of conductor tracks which form a lowermost conductor level and a second pattern of conductor tracks which form an uppermost 115 conductor level which is locally connected electrically to the lowermost conductor level and locally crosses the lowermost conductor level, in which at the area of the crossing the levels are isolated from each other 120 electrically, wherein, after providing the conductor pattern of the lowermost level, an intermediate layer is provided over the surface, which layer covers the conductor tracks of the lowermost conductor level 125 and the space between said conductor tracks and which is of a material which is electrically conductive, can be etched selectively with respect to the material of the lowermost conductor pattern and the 130 1 584756 material of the uppermost conductor pattern to be provided and can form a good adhesion with said materials, after which the conductor pattern of the uppermost level is provided on the intermediate layer and the intermediate layer is subjected to a selective etching treatment in which the conductor pattern of the uppermost level forms an etching mask and the intermediate layer is removed entirely at least at the area of the crossing by underetching the intermediate layer below the tracks of the uppermost conductor pattern forming the crossing and in which the intermediate layer at the areas of the electrical connection between the uppermost and lowermost conductor patterns is removed only partly by underetching of the intermediate layer below the tracks of the uppermost level, at least a part of the second pattern forming a conductive connection between two separated parts of the first pattern and via residual portions of the intermediate layer situated on said two separated parts of the first pattern.
In such a method the intermediate layer is subjected only to a single etching treatment, namely after providing the conductor tracks of the uppermost level A separate photoetching treatment before providing the uppermost conductor level for forming contact holes in the intermediate layer at the area of the connections between the various levels is not necessary.
The connections between the conductor levels are obtained in a self-registering manner with respect to the conductor tracks of the lowermost level As a result of this the mutual distances between said conductor tracks may be chosen to be very small This presents important advantages in connection with the packing density of the circuit.
A material which has proved particularly suitable for use for the intermediate layer is Ni Aluminium or multiple layers of Au with Pt and/or Ti may be used for the conductor patterns As will be described hereinafter, Ni can be etched selectively with respect to these materials Nickel also forms a good adhesion with the said materials In addition, Ni can generally be etched away more rapidly from the intermediate layer when it forms a shortcircuited couple with a noble metal.
For carrying out the method in accordance with the invention, various geometries may advantageously be used for the uppermost conductor level For example, the conductor tracks of the uppermost level may be provided at the area of the crossings with narrowings as a result of which the intermediate layer may be removedentirely at the area of the crossings while elsewhere parts of the intermediate layer are still present One form which permits of using high packing densities is one in which the conductor tracks of the second pattern, at the areas of the connections to the first pattern, are provided with widenings below 70 which the material of the intermediate layer is removed only partly during etching the intermediate layer.
Embodiments of the invention will now be described, by way of example, with 75 reference to the accompanying diagrammatic drawings, in which:Figure 1 is a plan view of part of a semiconductor device having a conductor pattern manufactured by using a method 80 in accordance with the invention; Figure 2 is a sectional view of said device taken on the line II-II of Figure 1; Figure 3 is a sectional view of the same device taken on the line III-III of Figure 85 1; Figures 4 to 6 are sectional views, taken on the line II-II of Figure 1, of the device during various stages of its manufacture; Figure 7 is a sectional view, taken on 90 the line III-III, of the device shown in Figure 1 in one of its manufacturing stages; Figure 8 is a sectional view of another semiconductor device manufactured by using a method in accordance with the 95 invention.
It is to be noted that the Figures are purely diagrammatic and are not drawn to scale.
The device shown in Figures 1 to 3 100 comprises a semiconductor body 1 in which a plurality of circuit elements, such as transistors, diodes, resistors, capacitors, and the like, are present in a conventional manner Such circuit elements are not 105 shown in the Figure and may be provided in the body 1 by means of generally known methods of manufacturing integrated circuits As is usually the case, the semiconductor body 1 is of silicon, although 110 other semiconductor materials may be used, if desired The circuit elements are situated near a surface which, as is known, is usually passivated with an insulating layer of, for example, silicon oxide The passi 115 vating layer is not shown in the Figures for reasons of clarity.
In order to connect the circuit elements together and to external supply conductors, the semiconductor body 1 has a conductor 120 pattern at its surface Said conductor pattern comprises a first set of conductive tracks 3 to 6 constituting a lowermost conductor level As is known, said tracks may be connected to the various zones of the 125 underlying circuit elements via contact windows in the said passivating layer.
A second pattern of conductor tracks 7, 8 and 9 is present above said lowermost conductor level and constituting an upper 130 1 584756 most conductor level The conductor tracks 7, 8 and 9 form connections to the conductor tracks 3 to 6 of the lowermost level.
For example, the conductor 7 which interconnects conductors 3 and 6 forms connections 10 and 11, respectively, to the conductors 3 and 6, respectively, of the lowermost level, while the conductor 8 in the part shown is connected only to the conductor 4 at the area of the connection 12 The connections 10 to 12 are shaded in Figure 1.
Since with respect to the surface 2 of the body the wiring 7 to 9 of the uppermost level is situated at a higher level than the conductor tracks 3 to 6 of the lowermost level, the tracks 7 to 9 can cross the conductor tracks 3 to 6 without being electrically short-circuited therewith The possibility of such crossings may be considered as a primary advantage of multilayer wirings because as a result of this the number of possible connections and hence the complexity of the integrated circuit can be increased.
In the plan view of Figure 1, the tracks 3 to 6 of the lowermost level are shown in broken lines at the area of the crossings which are referenced 13.
The manufacture of the device shown in Figures 1 to 3 will now be described with reference to Figures 4 to 7 Figures 4 to 6 are sectional views corresponding to the sectional view show shown in Figure 2 and taken on the line II-II of Figure 1 at various stages in the manufacture of the device Figure 7 is a sectional view corresponding to the sectional view shown in Figure 3 and taken on the line III-III of Figure 1 of the device during one of the steps during its manufacture.
Figure 4 shows the device in the stage in which the conductor tracks 3 to 6 of the lowermost level are provided on the surface 2 It is assumed that the various zones of the circuit have been formed in the semiconductor body 1 by means of known masked diffusion or implantation of the suitable impurities and that the surface 2 has been provided with a passivating layer or layers in which contact holes are formed Via said contact holes the tracks 3 to 6 can form contact with the various zones in the semiconductor body.
The conductor tracks 3 to 6 can be obtained by sputtering or evaporating on the surface 2 a layer of the conductor material of the conductor tracks and forming the conductor tracks therefrom by a photolighographic and etching treatment.
A suitable metal for the conductor tracks 3 to 6 is, for example, aluminium A specific thickness is approximately 0 5 micron The conductor tracks 3 to 6 can also be composed of a number of sub-layers of different metals For example, a suitable combination which can be used advantageously is formed by Pt with Ti and/or Au layers which has successively been provided one on the other Conductors of this 70 composition are known per se and can be obtained in known manner The width of the tracks 3 to 6 is approximately 7 microns, while the mutual distances between the tracks can be chosen in accordance with 75 the circuit.
In the next process step, see Figure 5, an intermediate layer 14 is provided which extends over the whole surface 2 and covers the conductor tracks 3 to 6 and the spaces 80 between said tracks For said intermediate layer a material is chosen which can be etched selectively with respect to the material or the materials which is or are used for the conductor patterns of the 85 uppermost and lowermost levels In addition, the material of the intermediate layer 14 should be electrically conductive and should be capable of forming a good adhesion with the materials of the uppermost 90 and the lowermost conductor levels A material which has proved to satisfy these requirements is, for example, nickel (Ni).
The thickness of the nickel layer 14 is not critical and is approximately 1 micron The 95 Ni can be grown mainly electrolytically after first a thin Ni layer (for example 100 A) has been vapour-deposited on the surface 2 of the body 1.
The conductor tracks 7 to 9 are then 100 provided on the intermediate layer 14 (Figure 6) For these tracks the same materials may be chosen as for the conductor tracks 3 to 6 of the lowermost conductor level For example, the tracks 7 105 to 9 may consist of Al; the tracks 7 to 9 may alternatively consist advantageously of multiple layerse such as Pt with Au or Pt with Ti and Au.
As shown in the plan view of Figure 1 110 and in the sectional view of Figure 3 the tracks 7 to 9 of the uppermost conductor level have widenings at the area of the crossings 10 to 12.
These widenings play an important part 115 during the subsequent etching treatment to which the intermediate layer 14 is subjected, as is shown in Figure 7 As an etchant is used, for example, a solution consisting of 3 vol of concentrated nitric acid (NHO 3) 120 and 7 vol of water at 50 WC This solution can etch the nickel of the intermediate layer 14 but substantially does not attack the Al or the Ti Au layers or Pt Au layers of the various conductor levels 125 For this etching treatment no separate photomasking step is necessary unlike conventional processes in which a layer should be removed locally The conductor pattern 7 to 9 of the uppermost conductor level 130 1 584756 itself is used as an etching mask, the etching liquid being contacted with the nickel of the intermediate layer 14 via the intermediate spaces between the conductors 7 to 9 of the uppermost conductor level.
The etching liquid attacks the intermediate layer 14 not only vertically but also laterally below the conductors 7 to 9.
This is denoted by the arrows 16 in Figure 7 The etching treatment is continued at least for such a period of time that the intermediate layer 14 has disappeared entirely below the conductors 7 to 9 of the uppermost conductor level except at the area of the widenings 15 With a width of the conductors 7 to 9 of approximately microns and a given etching rate, the etching treatment is continued, for example, until the distance over which the intermediate layer 14 is removed is approximately 3 microns Since the intermediate layer is attacked on either side of the conductors 7 to 9, the intermediate layer 14 below the conductors 7 to 9 will be removed entirely with the given width of the said conductors At the area of the crossings 13 the conductor levels are then electrically insulated from each other.
The intermediate layer 14 is underetched also at the area of the widenings 15 At this area, however, the intermediate layer 14 is removed only partly up to the boundaries shown in broken lines in Figure 7 As a result of this, below the widenings 15, which are situated in places where conductor tracks of the uppermost level should be connected electrically to conductor tracks of the lowermost level, separated parts of the intermediate layer 14 are obtained which form the connections to 12 between the various conductor levels When the width of the conductor tracks 10 to 12 at the area of the widenings is approximately twice the width of said tracks at the area of the crossings, thus approximately 12 microns, connections 10 to 12 will be formed having a width of approximately 6 microns.
It is to be noted that the connection parts 10 to 12 are formed in a selfregistering manner with respect to the conductor tracks 7 to 9 A separate photomasking step is not necessary In addition, the provision of the connections 10 to 12 hardly constitutes a restricting factor for the packing density The conductor tracks 7 to 9 can be positioned very close together since in the process described no critical alignment steps occur with respect to patterns previously provided in the intermediate layer 14 and with which steps some tolerance has to be allowed for.
By removing the nickel, the structure shown in Figures 2 and 3 is obtained The conductor tracks 7 to 9 form bridges which are separated effectively from the conductor tracks of the lowermost level at the area of the crossings 13 The possible occurrence of short-circuits between the conductor levels, as may often happen in conventional 70 multi-layer wiring systems in which the conductor levels are separated by an insulating oxide layer on which the uppermost level is deposited, is considerably lessened in this case The bridges are 75 supported by piers which are formed by the electrically conducting connections 10 to 12 which form a good adhesion with the conductor patterns of the various conductor levels 80 In the case in which the number of crossings 13 between two such piers is very large, the length of the bridge between said piers (connectors) may also become very large Figure 8 shows a possible solution 85 to prevent sagging of the bridge between two successive connections The sectional view shown in this Figure differs mainly therein from the device shown in Figure 2 by the larger number of conductor tracks of 90 the lowermost conductor level which are situated between the connections 10, 11 and which are crossed by the conductor 7 of the uppermost conductor level For illustration, the Figure shows, in addition to the con 95 ductors 3 and 4, also the further conductors 17, 18 which belong to the lowermost conductor level and are crossed by the conductor 7.
In order to prevent the conductor 7 100 sagging between the connections, the conductor 7 has an extra widening in the centre of the drawing between the tracks 17 and 18, which widening is shown diagrammatically by the lines 19 105 During etching the intermediate layer 14 a pier 20 is also formed below the widening 19 in addition to the forming of piers at the area of the connections between the various conductor levels The base of the 110 pier 20 bears directly on the surface of the support member 1 as contrasted with the connection parts 10, 11 which bear on a conductor track of the lowermost level.
Many variations are possible to those 115 skilled in the art without departing from the scope of this invention For example, the conductors of the uppermost level, instead of being constructed with widenings at the area of the connections, may alterna 120 tively be provided with narrowings at the area of the crossings so that at the area of the crossings the intermediate layer can be removed entirely by underetching whilst elsewhere parts of the intermediate layer 125 remain In places where the intermediate layer is to be removed entirely, for example at the area of the crossings, the conductor tracks of the uppermost level may also be provided with apertures so that the inter 130 1 584756 mediate layer can be removed entirely both from the sides of the conductor tracks and through said apertues and only partly at the area of the connections, while nevertheless the conductor tracks of the uppermost level may have the same width everywhere.
Besides by means of providing extra piers, sagging of conductor tracks of the uppermost level can also be prevented by providing below said tracks a suitable lacquer of synthetic resin after etching away the intermediate layer.
Prior to providing the intermediate layer, an insulating layer of, for example, silicon oxide, may also be formed above the conductor tracks of the lowermost level at the area of the crossings, which layer does not cover the tracks of the lowermost level at the area of the connections The provision of this insulating layer need not be critical.
The intermediate layer may then be provided over the whole surface of the body and the process may be further continued as in the previously described embodiments.
In this manner a structure can be obtained in which the conductor tracks of the lowermost level are separated from the uppermost level at the area of the crossings by the insulating layer and by an empty intermediate space Sagging of tracks of the uppermost level will then not give rise to short-circuits.

Claims (9)

WHAT WE CLAIM IS: –

1 A method of manufacturing a semiconductor device comprising a semiconductor body having at one of its surfaces a plurality of regions forming a first pattern to which regions there are electrically connected a plurality of conductor tracks forming a second pattern, wherein after providing the first pattern an intermediate layer is provided over the surface, said intermediate layer consisting of a material which is electrically conductive, can be etched selectively with respect to the material of the conductor tracks of the second pattern to be provided, and can form a good adhesion with the first pattern and the material of the conductor tracks of the second pattern to be provided, after which the conductor tracks of the second pattern are provided on the intermediate layer and the intermediate layer is subjected to a selective etching treatment in which the tjacks of the second pattern form an etching mask and the intermediate layer is locally removed entirely by underetching of the intermediate layer below the tracks of the second pattern and in which the intermediate layer at least at the areas of the connections between the conductor tracks of the second pattern and the regions of the first pattern is removed only partly by underetching below the tracks of the second pattern, at least a part of the second pattern forming a conductive connection between two separated parts of the first pattern and via residual portions of the intermediate layers situated on said two separated parts of the first pattern 70

2 A method of manufacturing a semiconductor device having a semiconductor body which is provided at one of its surfaces with a conductor pattern comprising a first pattern of conductor tracks which form 75 a lowermost conductor level and a second pattern of conductor tracks which form an uppermost conductor level which is locally connected electrically to the lowermost conductor level and locally crosses the lower 8 G most conductor level, in which at the area of the crossing the levels are isolated from each other electrically, wherein, after providing the conductor pattern of the lowermost level, an intermediate layer is provided 85 over the surface, which layer covers the conductor tracks of the lowermost conductor level and the space between said conductor tracks and which is of a material which is electrically conductive, can be etched 90 selectively with respect to the material of the lowermost conductor pattern and the material of the uppermost conductor pattern to be provided and can form a good adhesion with said materials, after which the 95 conductor pattern of the uppermost level is provided on the intermediate layer and the intermediate layer is subjected to a selective etching treatment in which the conductor pattern of the uppermost level forms an 100 etching mask and the intermediate layer is removed entirely at least at the area of the crossing by underetching the intermediate layer below the tracks of the uppermost conductor pattern forming the crossing and 105 in which the intermediate layer at the areas of the electrical connections between the uppermost and lowermost conductor patterns is removed only partly by underetching of the intermediate layer below the 110 tracks of the uppermost level, at least a part of the second pattern forming a conductive connection between two separated parts of the first pattern and via residual portions of the intermediate layer situated 115 on said two separated parts of the first pattern.

3 A method as claimed in Claim 1 or Claim 2, wherein the conductor tracks of the second pattern, at the areas of the con 120 nections with the first pattern, are provided with widenings below which the material of the intermediate layer is removed only partly during etching the intermediate layer.

4 A method as claimed in Claim 3, 125 where appendant to Claim 2, wherein the conductor tracks of the uppermost conductor level, at the area of the connections with the conductor tracks of the lowermost conductor level, are provided with widen 130 1 584756 ings so that the width of a conductor track of the uppermost conductor level at the area of such a connection is at least twice the width of a conductor track of the uppermost conductor level at the area of a crossing.

A method as claimed in any of the preceding Claims, wherein the intermediate layer is formed from nickel.

6 A method as claimed in Claim 5, wherein at least one of the first and second patterns is manufactured from aluminium (Al).

7 A method as claimed in Claim 6, wherein at least one of the first and second patterns is provided as a multiple layer of which one layer is formed by Au and a second layer is formed by a metal selected from the group Pt and Ti.

8 A method of manufacturing a semi 20 conductor device substantially as herein described with reference to Figures 1 to 7, or Figure 8 of the accompanying drawings.

9 A device when manufactured by using a method as claimed in any of the preced 25 ing Claims.
R J BOXALL, Chartered Patent Agent, Mullard House, Torrington Place, London WC 1 E 7 HD.
Agent for the Applicants.
Printed for Her Majesty’s Stationery Office by The Tweeddale Press Ltd, Berwick-upon-Tweed, 1980.
Published at the Patent Office, 25 Southampton Builldings, London, WC 2 A l AY, from which copies may be obtained.

GB33136/77A
1976-08-11
1977-08-08
Methods of manufacturing devices including a pattern of conductor tracks

Expired

GB1584756A
(en)

Applications Claiming Priority (1)

Application Number
Priority Date
Filing Date
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NL7608901A

NL7608901A
(en)

1976-08-11
1976-08-11

PROCESS FOR THE MANUFACTURE OF A SEMI-CONDUCTOR DEVICE AND SEMIC-CONDUCTOR DEVICE MANUFACTURED BY SUCH PROCESS.

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GB1584756A
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GB1584756A
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1981-02-18

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GB33136/77A
Expired

GB1584756A
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1976-08-11
1977-08-08
Methods of manufacturing devices including a pattern of conductor tracks

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JPS5837992B2
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AU
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AU509242B2
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CA1090477A
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CH617037A5
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DD
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DD132091A5
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DE
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DE2734176A1
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FR
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FR2361745A1
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GB
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GB1584756A
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HU
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HU176861B
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IT
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IT1086058B
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NL
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NL7608901A
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PL
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GB2178896A
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1985-07-19
1987-02-18
Plessey Co Plc
A method of producing a layered structure

GB2280545A
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1993-07-27
1995-02-01
Samsung Electronics Co Ltd
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1987-09-16
Philips Nv

METHOD FOR MANUFACTURING A WIRING SYSTEM, AND A SEMICONDUCTOR DEVICE EQUIPPED WITH SUCH WIRING SYSTEM.

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1983-09-23
1985-04-16
Philips Nv

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MADE BY THE USE OF SUCH A METHOD

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1976

1976-08-11
NL
NL7608901A
patent/NL7608901A/en
not_active
Application Discontinuation

1977

1977-07-29
DE
DE19772734176
patent/DE2734176A1/en
not_active
Ceased

1977-08-04
CA
CA284,097A
patent/CA1090477A/en
not_active
Expired

1977-08-05
SU
SU772508749A
patent/SU673206A3/en
active

1977-08-08
DD
DD7700200484A
patent/DD132091A5/en
unknown

1977-08-08
JP
JP52094277A
patent/JPS5837992B2/en
not_active
Expired

1977-08-08
IT
IT26589/77A
patent/IT1086058B/en
active

1977-08-08
PL
PL20012777A
patent/PL200127A1/en
unknown

1977-08-08
CH
CH971177A
patent/CH617037A5/de
not_active
IP Right Cessation

1977-08-08
SE
SE7708968A
patent/SE7708968L/en
unknown

1977-08-08
GB
GB33136/77A
patent/GB1584756A/en
not_active
Expired

1977-08-08
AU
AU27698/77A
patent/AU509242B2/en
not_active
Expired

1977-08-09
HU
HU77PI588A
patent/HU176861B/en
unknown

1977-08-10
FR
FR7724603A
patent/FR2361745A1/en
active
Granted

1979

1979-03-02
US
US06/016,843
patent/US4308090A/en
not_active
Expired – Lifetime

Cited By (3)

* Cited by examiner, † Cited by third party

Publication number
Priority date
Publication date
Assignee
Title

GB2178896A
(en)

1985-07-19
1987-02-18
Plessey Co Plc
A method of producing a layered structure

GB2280545A
(en)

1993-07-27
1995-02-01
Samsung Electronics Co Ltd
A highly integrated semiconductor wiring structure

GB2280545B
(en)

1993-07-27
1997-08-13
Samsung Electronics Co Ltd
A highly integrated semi-conductor wiring structure and a method for manufacturng the same

Also Published As

Publication number
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PL200127A1
(en)

1978-04-24

AU2769877A
(en)

1979-02-15

CA1090477A
(en)

1980-11-25

CH617037A5
(en)

1980-04-30

HU176861B
(en)

1981-05-28

SE7708968L
(en)

1978-02-12

AU509242B2
(en)

1980-05-01

JPS5837992B2
(en)

1983-08-19

US4308090A
(en)

1981-12-29

JPS5321587A
(en)

1978-02-28

FR2361745B1
(en)

1983-06-03

FR2361745A1
(en)

1978-03-10

DE2734176A1
(en)

1978-02-16

NL7608901A
(en)

1978-02-14

IT1086058B
(en)

1985-05-28

DD132091A5
(en)

1978-08-23

SU673206A3
(en)

1979-07-05

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